An investigation of input protection for CDM robustness in 40nm CMOS technology

Adiabatic failures due to an initial peak voltage of VF-TLP measurements were observed at the input gate of a 40 nm CMOS technology. Moreover, a correlation was verified between the failure current of the VF-TLP measurements and failure voltage of CDM testing. Through the transient analyses by a VF-TLP system, the performance of a diode-stack was better than that of SCRs as an input protection for CDM robustness.