Thermal analysis of hot spots in advanced 3D-stacked structures

3D integration architectures for microelectronic circuits have attracted much interest in the recent past, due to their capabilities for more efficient device integration and faster circuit operation. This type of assembly is formed by bonding multiple active layers through a dielectric material, and employs through-silicon vias for electrical interconnection. In this work we present the thermal analysis of a typical 3D-stack, performed by finite element simulations. The effect of the variation of various parameters on the area of influence of a hot spot and on the overall temperature in the stack has been analyzed. We have also investigated the thermal impact of copper studs in the dielectric: the results suggest that Cu studs with a small pitch in the glue can efficiently reduce the temperature in the Si dies.