A simulated annealing based technology mapping method for sequential circuits

Due to the rapid growth of traffic in Internet, backbone links of 40 gigabits per second are commonly deployed. To handle high traffic rates, the backbone routers must be able to forward millions of packets per second on each of their ports. Pipelined design can effectively support high speed packets processing. Technology mapping method for sequential circuits in FPGA is playing vital role to pipelined design. This paper presents a simulated annealing based technology mapping method for sequential circuits. The proposed method not only guarantees minimal clock period for pipeline level, but also saves FPGA resources.