Soft error robust impulse and TSPC flip-flops in 90nm CMOS

We propose an impulse flip-flop and a true single-phase clock (TSPC) flip-flop that are soft error robust. Each flip-flop consists of a unique transfer unit and a soft error robust 8-transistor Quatro latch. The transfer unit of the impulse flip-flop uses the clock signal and its complement to generate a narrow voltage pulse that enables writing the data into the Quatro latch. In contrast, the transfer unit of the TSPC flip-flop uses only the clock signal to conditionally pass the data into the Quatro latch. The flip-flops exhibit as much as 56% lower power-delay product when compared with a recently reported soft error robust flip-flop. The maximum area overhead of the proposed flip-flops is only 10% with respect to a master-slave D flip-flop. Post-layout simulations in 90nm CMOS technology confirms the functionality of the proposed flip-flops while an accelerated radiation test on an SRAM chip shows 47x lower soft error rate in the Quatro latch used in the proposed flip-flops.