On-Chip Interconnect Analysis of Performance and Energy Metrics Under Different Design Goals

As semiconductor process technology scales down, interconnect planning presents ever-greater challenges to designers. In this paper, we analyze, evaluate, and compare various metrics with optimized wire configurations in the contexts of different design criteria: delay minimization, delay-power minimization, and delay
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-power minimization. We show how various design criteria influence the configuration, performance, and power consumption of repeated wires.