A low-power area-efficient 8 bit SAR ADC using dual capacitor arrays for neural microsystems

We report an area-efficient 8 bit SAR ADC using dual capacitor array banks for brain signal interface microsystems. The proposed ADC consumes 680 nW and the total chip area is 0.035 mm
²
. We reduced the area and power by a factor of eight when compared with conventional approaches. If we increase the resolution, the area and power reduction factor exponentially increases in our architecture (e.g., a factor of 16 for 10 bit resolution). The measured SNDR, SFDR, THD, and ENOB are 42.82 plusmn 0.47 dB, 57.90 plusmn 2.82 dB, -53.58 plusmn 2.15 dB, and 6.65 plusmn 0.07 bits, respectively.