Comparison of VLS grown Si NW tunnel FETs with different gate stacks

In the present work we demonstrate the fabrication of tunneling field-effect transistors (TFETs) based on VLS grown silicon nanowires (Si NWs). We have integrated two different gate stacks, a conventional one using SiO
₂
and a HfO
₂
high-k gate stack. The use of a high-k gate dielectric markedly improves the TFET performance in terms of average slope and on-current, I
_on
. Furthermore, we investigate the low-temperature behaviour of the TFETs.