A zero VTH memory cell ferroelectric-NAND flash memory with 32% read disturb, 24% program disturb, 10% data retention improvement for enterprise SSD

A zero V
_TH
memory cell scheme for the ferroelectric (Fe)-NAND flash memory is proposed. In the zero V
_TH
memory cell scheme, the middle of V
_TH
of erased and programmed cells is 0 V. Based on the measurement, this paper shows for the first time that the reliability of a Fe-NAND cell such as the data retention, read disturb, and program disturb is best optimized in the proposed zero V
_TH
cell. The measured V
_TH
shift due to the read disturb, program disturb and data retention decreases by 32%, 24% and 10%, respectively. Contrarily, in the negative V
_TH
cell where the middle of V
_TH
of erased and programmed cells is negative, the V
_TH
shift during the data retention is as much as 0.49 V and unacceptably large. In the conventional positive V
_TH
cell where the middle of V
_TH
of erased and programmed cells is positive suffers from a sever read and program disturb. The measured results are drastically different from those of the conventional floating-gate NAND cell where the negative V
_TH
cell is most suitable in terms of the reliability.