Comparison of double patterning technologies in NAND flash memory with sub-30nm node

Fine patterning technologies - e-beam lithography, SPT (spacer patterning technology) and SaDPT (self aligned double patterning technology)-have been introduced to develop a single unit of nano-scale MOSFET. However, in order to achieve manufacturable high density NAND Flash memories, the merits and demerits of each technology should be considered in three points of view: device characteristics, process controllability and mass production. In this paper, we suggest the appropriate technology for particular cell types, CTF (charge trap flash) cell, floating poly-Si gate cell, and for process steps such as active, gate and bit-line.