A 200 µA duty-cycled PLL for wireless sensor nodes

A duty-cycled PLL operating in burst mode is presented. It is an essential building block of a moderately accurate low-power frequency synthesizer suitable for use in nodes for wireless sensor networks. Once in lock, the PLL's frequency error is less than 0.1% (rms). Fabricated in a baseline 65 nm CMOS process, the PLL occupies 0.19 times 0.15 mm
²
and draws 200 muA from a 1.3-V supply when generating a 1 GHz signal with a duty cycle of 10%.