Design of 5.8 GHz Dielectric Resonator Oscillator Applied in Electronic Toll Collection

In the electronic toll collection (ETC) application, the dielectric resonator oscillator (DRO) must exhibit low phase noise in order to meet bit error rate requirements. It also should provide enough output power to directly drive the mixer. This paper designs the DRO in the 5.8 GHz by negative resistance theory and harmonic balance theory with use of Agilent advance design system (ADS) tool. The dielectric resonator is modeled as a package of cResP in ADS. After the simulation and optimization of the nonlinear models of the DRO, the satisfying result was found. At @ 5.8 GHz, the output power was exhibited exceed 10 dBm, phase noise was less than -95 dBc.