Compact modeling of stress effects in scaled CMOS

Strained Si is implemented into the standard CMOS process to enhance carrier transport properties since the 90 nm technology node. However, due to the non-uniform stress distribution in the channel, the enhancement of carrier mobility and threshold voltage strongly depend on layout parameters, such as channel length (L) and source/drain diffusion length (L
_sd
). In this work, a compact model that physically captures these behaviors is developed for circuit simulation with strained CMOS technology.