Analysis and optimization of LUDMOS transistors on a 0.18µm SOI CMOS technology

This paper is focused on the design and optimization of power LDMOS transistors (V
_BR
> 120 Volts) with the purpose of being integrated in a new generation of Smart Power technology based upon a 0.18 mum SOI-CMOS technology. The benefits of applying the shallow trench isolation (STI) concept along with the 3D RESURF concept in the LDMOS drift region is analyzed in terms of the main static (R
_on-sp
/V
_BR
trade-off) and dynamic (Miller capacitance and Q
_g
timesR
_on
FOM) characteristics. The influence of some design parameters such as the polysilicon gate electrode length and the STI length are exhaustively analyzed.