Integrated circuit with tunable bandwitdh for neural signal recording

We present the architecture and preliminary measurements of an ASIC for neural signal recording. The chip consists of 64 analogue channels followed by the analogue multiplexer and it is fabricated in the 180 nm CMOS technology. It consumes 220 µW per channel from ±0.9 V power supply and occupies 13 mm
²
area. User is capable to modify frequency bandwidth in the 1 Hz – 60 Hz range for low cut-off frequency and 3.5 kHz – 15 kHz for high cut-off frequency. All measured parameters confirm the designed integrated circuit may be successfully used in neurobiology tests.