Multiprocessor design verification for the PowerPC 620 microprocessor

Multiprocessor design verification for the PowerPC 620 microprocessor was challenging due to the 620 Bus protocol complexity. The highly concurrent bus and level 2 (LS) cache interfaces, and the extensive system configurability. In order to verify this functionality, a combination of random and deterministic approaches were used. The Random Test Program Generator (RTPG) and the newly developed Stochastic Concurrent Program Generator (SCPG) tools were used for random verification. In the deterministic front, testcases in C were written to verify specific scenarios. In creating SCPG, we dealt with the design complexity and frequent design changes by abstracting areas of concern as simple languages, writing tools to generate tests, and executing these in the standard verification environment. The added value of these tests is that they exercise true data sharing among processors, are self-checking and resemble commercial multiprocessor code.