Inductance calculation and optimal pin assignment for the design of pin-grid-array and chip carrier packages

A methodology for the calculation of self- and mutual inductance of various electrical paths in a pin-grid array (PGA) or a chip carrier package is described. An N*N inductance matrix is generated for a package, where N is determined by the number of pins, power, and ground planes. Theory, algorithms, and software have been developed to compute the effective inductance of multiply coupled inductors. The software estimates the number of pins for a specified value of inductance and computes the effective inductance for sets of pins chosen for various functions. In this manner, several groups of pin assignments can be evaluated to obtain the smallest effective inductance. The design software computes a 132*132 inductance matrix in about 45 min on an HP 9040 computer. Illustrative examples of pin assignments for power and ground pins in single- and multilayer packages are provided. Good agreement between calculation and experiment was found for packages with pin counts varying from 68 to 289. Design guidelines for pin assignments and placement of power distribution planes in a single- or multilayer package are given for low-inductance package design.<
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