Variation-Aware System-Level Power Analysis

The operational characteristics of integrated circuits in nanoscale semiconductor technology are expected to be increasingly affected by variations in the manufacturing process and the operating environment. In this paper, we address the problem of incorporating the effects of variations into system-level power analysis tools. We consider both manufacturing-induced (die-to-die and within-die) variations in device characteristics, and operation-induced dynamic variations in on-chip temperature. To motivate our work, we first analyze the impact of variations on the power consumption of an example System-on-Chip (SoC). We show how simple extensions of current approaches to system-level power estimation (based on spreadsheets or system-level simulation) are not well-suited to performing variation-aware power-estimation. We propose a system-level power estimation methodology that accurately and efficiently analyzes the impact of variations on SoC power consumption. The proposed methodology combines fast trace analysis, power-state based leakage modeling, efficient thermal analysis, and Monte Carlo sampling to generate SoC power distributions, and power variability traces over time. The key benefit of the methodology is that it captures critical inter-dependencies between component workload profiles, leakage power, and variations in temperature and device parameters, while avoiding time-consuming iterative simulations. Our implementation of the proposed methodology within an in-house system-level power estimation framework indicates speedups of up to 4 orders of magnitude with negligible loss in accuracy as compared to Monte Carlo techniques. We also illustrate the application of our analysis framework can be used to explore a new class of “variation-aware” system-level power management techniques.