Design of a terabit free-space photonic backplane for parallel computing

The design of a terabit free-space photonic backplane for parallel computing and communications is described. The backplane consists of a large number of parallel reconfigurable optical channels spaced a few hundred microns apart. The parallel channels are organized as a unidirectional ring and the channel access protocols are implemented by smart pixel arrays. Smart pixel arrays are integrated optoelectronic devices with optical I/O and with electronic processing capabilities. The design of a 32/spl times/32 smart pixel array which supports multiple reconfigurable broadcast channels and interfaces between tens of Gb/s of electrical data and hundreds of Gb/s of optical data is proposed. The photonic backplane interconnects 32 printed circuit boards (PCBs) and has a bisection bandwidth of 1 terabit/sec (Tb/s), with each PCB receiving a bandwidth of 32 Gb/s. The backplane can be dynamically reconfigured to support 1024 broadcast channels at 1 Gb/s, 32 broadcast channels at 32 Gb/s, or many intermediate values. The backplane can also embed arbitrary graphs, including meshes, hypercubes, shuffles, etc. Smart pixel arrays are currently being fabricated using AT&T's Hybrid SEED process, and a demonstration of the architecture interconnecting 4 PCBs is planned for the fall of 1995.