A Generic Scalable Architecture for Min-Sum/Offset-Min-Sum Unit for Irregular/Regular LDPC Decoder

The most common algorithm used in iterative decoding of low-density parity check (LDPC) codes is based on a generic class of the sum-product algorithm, which has a nonlinear dependence on the log(tanh()) function. The implementation based on fixed precision has substantial loss of accuracy and is computationally expensive with full precision. A suboptimal version of belief propagation called the
offset-min-sum
algorithm is generally used in hardware implementation. This paper proposes a generic scalable architecture for minimum search during check-node operation in the
offset-min-sum
algorithm applicable to regular as well as irregular LDPC codes with check node of any degree
d
. For an LDPC code with maximum check node degree
d
, the proposed architecture consists of 2(
d
-2) 2 × 1 multiplexers and 3(
d
-2) two-input compare-and-select units (CSUs). This has latency of [2⌈log
₂
(
d
)⌉-2]
tdc
when ⌈log
₂
(
d
)⌉-log
₂
(
d
) <; log
₂
(4/3) else [2⌈log
₂
(
d
)⌉-3]
tdc
, with
tdc
representing the delay of a two-input CSU. The proposed architecture has been implemented for
d
= 20 using a TSMC 0.18-μm CMOS process.