Residual charge on the faulty floating gate CMOS transistor

A common defect that can occur in CMOS integrated circuits is a break in a signal track. The effect of this defect is strongly dependent on the amount of charge trapped on the isolated MOS transistor gate. Results of measurements on test structures are presented which reveal a range of values for the trapped charge. This causes the resulting fault to have a widely varying effect on circuit performance. A test strategy which guarantees detection of such faults is proposed.