The VHDL based design of the MIDA MPEG1 audio decoder

This paper describes the features and design methodology of MIDA, an MPEGI integrated audio decoder. MIDA has been almost completely designed using automatic synthesis of VHDL descriptions, and has been implemented using a cell based approach and a 0.7 /spl mu/m, 2 metal layers CMOS technology. The die area is 95 mm/sup 2/. Synthesis tools have also been used for automatic insertion of test structures and automatic test pattern generation.