An effective system development environment based on VHDL prototyping

This paper presents the use of VHDL prototyping as an effective basis for developing electronic (hardware and software) systems VHDL simulation is the platform on which a distributed environment for debugging the hardware and the software, that is running on the VHDL prototype, is built. To do it, the natural monitoring and observing facilities provided by a commercial VHDL simulator have been enhanced. The new environment supports the development of the complete system from the different points of view corresponding to the involved domains. To ease the task of creating a virtual prototype of the hardware, an enhancement of the natural configuration capabilities of VHDL, is also provided by a complementary tool that helps to build the prototype. The use of this new environment implies a new ESDA methodology.