Design and implementation of an improved 3G turbo codes interleaver for 3GPP system

Interleaver is important part in turbo encoder and decoder. The special third generation (3G) interleaver had been included in the released 3rd Generation Partnership Project (3GPP) specification and standard. The complex interleaver algorithm is described first. Then Verilog HDL Implementation of an improved interleaver is presented. By using RAM block, interleaver algorithm is transformed to address controlling of RAM reading and writing in order to simplify interleave process. It shows that encoding and decoding delay can be shorted effectively. The design was proved correctly by experiment and had been made use of in turbo encoder and decoder as a module.