High-level programming of coarse-grained reconfigurable architectures

Embedded signal processing systems are facing the challenges of increased computational demands. Reconfigurable architectures, which can be configured to form application-specific hardware, offer not only high degree of parallelism but also the possibility to dynamically allocate the resources during run-time. This allows the user to implement applications which are otherwise too large to be handled by a particular device. The reconfigurable computing devices have evolved over the years from the gate-level arrays to a more coarse-grained composition of highly optimized functional blocks or even program controlled processing elements, which are operated in a coordinated manner to improve performance and energy efficiency.