TLP analysis of 0.125 μm CMOS ESD input protection circuit

In this investigation, TLP ESD analysis shows that if a large input resistor is used in combination with a ggNMOS clamp in the input protection circuitry, then the trigger voltage, Vt1, of the ggNMOS increases. More importantly, the HBM injected current required to trigger snapback, It1, is significantly increased which unexpectedly delays the trigger of the ggNMOS secondary clamp and exposes the input receiver's thin gate oxide to excessive input pad stress voltages which results in 1-2 kV HBM leakage failures.