5-V tolerant fail-safe ESD solutions for 0.18µm logic CMOS process

Failsafe, high voltage tolerant, low capacitive ESD solutions are implemented in a 0.18 mum dual- gate advanced CMOS technology. This technology features a drain-extended transistor with BVdss of 13 V. Protection of drain extended transistors that allow up to 7V drain operating voltage using 70Aringring oxide is investigated with the integration of a special ldquoself-alignedrdquo STI-blocked SCR structure. Excellent HBM and CDM performance for the I/O applications with this approach are demonstrated.