VLSI architecture design for Inverse-CABAC on H.264 Decoder

This paper describes architecture design for Inverse-CABAC which is used for decoding entropy on H.264 Decoder. The architecture design refer to JM 11.0 program in C language that was designed by Joint Video Team from MPEG and ITU. This reference program also produces test vectors as a reference input and output for verification purposes. The result of the Inverse CABAC module proves that system functionality is verified. The design has also successfully synthesized with the FPGA device target, which is Virtex-4 XC4VSX35-10F668. The design has 278749 equivalent gate counts with the maximum working frequency is 118 MHz. For 100 MHz working frequency, the Inverse CABAC design has 10,43 Mbps throughput.