Effects of stress-induced mismatches on CMOS analog circuits

Degradation of element matching in CMOS analog circuits due to piezoresistive effects is discussed. The piezoresistive behavior of resistors is reviewed, and the response of CMOS devices to die stress is compared to the variation of resistors in CMOS technology. Theory and experimental results for stress induced changes in device parameters, matching in differential pairs and current mirrors and the offset voltage of CMOS op-amps are presented. General layout considerations for minimizing the response of CMOS analog circuits to die stress are discussed.