DRAM technology trend

During the last few years new DRAM products have been introduced at a rate of -4 years/generation instead of 3. This trend will continue. Chip design efficiency (defined as the ratio between cell and total chip area) must be increased to >60-65% for 1 Gb and beyond. Self-alignment schemes are essential for 64 Mbit and beyond but after the first generation of 1 Gb additional technology breakthroughs are needed for a cell area of less than 8F/sup 2/ where F is design size. Conventional nitride storage dielectric, in conjunction with capacitor area enhancement techniques like HSG (hemispheric grain) and corrugated cylindrical poly electrodes, is applicable for 256 Mbit and possibly first generation 1 Gb. Barium strontium titanate will be used for 1 Gb products and beyond.