Si-MOSFET scaling down to deep-sub-0.1-micron range and future of silicon LSI

The tremendous progress made with silicon LSIs over the past 25 years has been driven by the miniaturization of MOSFETs. Down-sizing MOSFETs below the 0.1 micron range, however, is proving technologically very difficult due to certain physical limitations. In this paper, we will demonstrate certain ways in which MOSFETs can be taken down to the deep-sub-0.1 micron regime, and also give our views on future LSIs using these MOSFETs.