Characterization and design of a low-power, high-performance cache architecture

We present results of characterization of power dissipation in on-chip cache memories. Details of power dissipated in different sub-circuits are presented. These results reveal that the memory peripherals and bit array dissipate comparable power. To optimize performance and power of a processor's cache, a multi-divided module (MDM) cache architecture is proposed to save power at memory peripherals as well as the bit array. Comparisons of MDM with conventional cache architectures for energy utilization and performance are presented.