On the bus arbitration for MPEG 2 video decoder

A bus arbitration scheme for the MPEG-2 video decoder VLSI developed by NCTU is proposed in this paper. Compared to the traditional pure stochastic bus scheduling scheme, the internal buffer requirement and bus arbitration overheads are reduced due to the deterministic nature of this strategy. This bus arbitration scheme has been verified using a Verilog simulator and will be implemented in the NCTU MPEG-2 decoder.