Timing analysis for synthesis of hardware interface controllers using timed signal transition graphs

The work addresses the design of hardware interface controllers for microprocessor-based systems. Interface design is required during the system integration phase to interconnect components which may use different interfacing protocols. It is shown that both the component interfacing protocols and the interface design can be described using an interpreted timed Petri net. Traditionally verification of the design is performed after the design has been synthesized. Such an approach usually requires several iterations, if the implementation violates some of the design constraints. A symbolic timing analysis is proposed to alleviate this problem: tight bounds on the interface path delays are computed using the available information from the protocol specifications prior to interface implementation. This is possible because our model can describe both circuit delays and environmental timing constraints. An example involving bus arbitration in the VMEbus is used to illustrate the analysis technique.