Modeling the impact of 3-D-technology on the performance of the memory hierarchy of RISC systems

In this paper we investigate 3-D-technology for improving the performance of the memory hierarchy of RISC based systems from an architectural point of view. It is assumed that using 3-D-technology, not only the processor and the first-level cache can be integrated onto one IC, but processor, first-level, and second-level cache may be integrated onto one 3-D IC. In addition, the cache may be organized in three levels. Results show, that for a given total cache size the performance in terms of the average time per instruction is improved by 20-35% depending on cache organization.