Use of symbolic analysis in analog circuit synthesis

A flexible and efficient program for the optimal sizing of analog integrated circuits is presented. The circuits are modeled with symbolic equations that are derived automatically by a symbolic simulator. The advantages and limitations of symbolic analysis for this application are investigated. Before optimization, the equations are ordered symbolically and then compiled in a way as minimize the overall evaluation time. The optimization tool then determines all device sizes and biasing for the circuit to meet the specifications while minimizing a user-defined cost function. Experimental results on realistic analog circuits show the efficiency of the approach.