Data-path testability analysis based on BDDs

Optimal application of Design for Testability techniques extends on an efficient testability analysis. Circuit complexity does not allow traditional testability analysis approach to perform efficiently. Therefore an higher abstraction level must be considered. This paper presents a methodology for controllability and observability verification at a functional level, starting from a VHDL description of the system architecture. Since efficiency is a primary goal for industrial application of such technique, a representation based on Binary Decision Diagrams has been introduced and its effectiveness is presented on telecom applications.