High-performance and low-bandwidth architecture of H.264 motion estimation circuit for 1080HD video

This paper presents a high-performance and low-bandwidth architecture of H.264 integer-pixel motion estimation circuit for 1080HD video. The proposed circuit supports 7 kinds of variable block sizes and generates 41 motion vectors. We propose a new motion estimation algorithm and circuit architecture to improve the processing speed and reduce the memory bandwidth. The implemented circuit based on the proposed algorithm and architecture can process 60 image frames per second for 1080HD video at the operating frequency of 45.5 MHz with smaller bandwidth requirement compared to other approaches.