A Wideband PLL-Based G/FSK Transmitter in 0.18 $\mu$m CMOS

A wideband phase-locked loop (PLL)-based G/FSK transmitter (TX) architecture is presented in this paper. In the proposed TX, the G/FSK data is applied outside the loop; hence, the data rate is not constrained by the PLL bandwidth. In addition, the PLL remains locked all the time, preventing the carrier frequency from drifting. In this architecture, the G/FSK modulation signal is generated from a proposed Sigma-Delta modulated Phase Rotator $(\Sigma\Delta{\hbox{-PR}})$. By properly combining the multi-phase signals from the PLL output, the $\Sigma\Delta{\hbox{-PR}}$ effectively operates as a fractional frequency divider, which can synthesize modulation signals with fine-resolution frequencies. The proposed $\Sigma\Delta{\hbox{-PR}}$ adopts the input signal as the phase transition trigger, facilitating a glitch-free operation. The impact of the $\Sigma\Delta{\hbox{-PR}}$ on the TX output noise is also analyzed in this paper. The proposed TX with the $\Sigma\Delta{\hbox{-PR}}$ is digitally programmable and can generate various G/FSK signals for different applications. Fabricated in a 0.18 $\mu\hbox{m}$ CMOS technology, the proposed TX draws 6.3 mA from a 1.4 V supply, and delivers an output power of $-$11 dBm. With a maximum data rate of 6 Mb/s, the TX achieves an energy efficiency of 1.5 nJ/bit.