Characteristics of DNRO ferroelectric FETs with a Poly- Si floating gate

Non-destructive read out memory FET using ferroelectric gate insulator has been developing remarkably and device such as to use buffer layer has been requiring for high process technology. But it is very difficult to deposit on buffer layer the same as deposition directly on Si. After making FET by deposition of ferroelectric on prepared floating gate, our evaluation carried out. This FET is MFMIS structure which consists of Si-sub, gate Si0
₂
, floating gate, PZT and control gate electrode in order from the bottom. PZT was deposited at the Zr/Ti (=52/48) ratio by sol-gel method. Polycrystalline silicon (poly-Si) was used as floating gate which was ferroelectric bottom electrode. Ir0
₂
and Ir and other materials coated on the poly-Si for ferroelectric deposition. We succeeded in deposition of PZT with good ferroelectricity, because IrO
₂
and Ir can prevent Pb and other elements from diffusing into poly-Si and gate Si0
₂
. Memory effect of this FET was confirmed.