An Experimental Ultra-Low-Voltage Demodulator in 0.18-$\mu$ m CMOS

An experimental demodulator suitable for ultra-low-voltage and low-power wireless applications is presented in this paper. To alleviate the stringent design constraints, discrete-time frequency-shift keying (FSK) is employed in this design. The proposed demodulator is composed of limiting amplifiers (LAs), low-pass filters (LPFs), and discrete-time quadricorrelators. For circuit implementations, negative-feedback source-degeneration gain cells are adopted in the LAs for low-voltage operations, while the LPFs are realized by a Sallen-Key structure with differential difference amplifiers for reduced power consumption and chip area. As for the quadricorrelators, delay cells are utilized in the discrete-time differentiator and the baseband signals are finally detected for logic recognition. Using a standard 0.18-mum CMOS process, the proposed demodulator is implemented for demonstration. Operated at a 0.6-V supply voltage, the fabricated circuit consumes a dc power of 2.4 mW. With a data rate of 1 Mb/s and a modulation index of 0.32, the measured bit error rates for FSK and Gaussian FSK schemes are 0.333% and 1.036%, respectively, at an IF frequency of 2 MHz.