Submicrosecond Core Memories Using Multiple Coincidence

Memories using toroidal ferrite cores with cycle timies less than a microsecond are described; the selection ratio is increased by the use of biasing and the multiple coincidence principles of Minnick and Ashenhurst.1 It is shown that this mode of operation leads to important changes in the structure of the store; in particular, the classical core switch does not fulfll the new requirements. The ``two-core switch'' is then briefly described; it permits an elegant and economic solution of the problems arising at high selection ratios. Details of the design and operation of memories embodying these ideas are given; it is shown, for example, that standard core memory matrices can be used very efficiently at a selection ratio of 3:1 to achieve a cycle time of 2 microseconds. Further illustrations are given from a model of a 100×100 store operated at 4:1 and 7:1 selection ratios, and it is shown that a store of 10,000 8-bit characters with a cycle time of 0.25 microsecond is feasible.