New CMOS logarithmic A/D converters employing pipeline and algorithmic architectures

New techniques for realizing CMOS logarithmic analog-to-digital (A/D) converters employing pipeline and algorithmic architectures are described. This is achieved by replacing the operations of subtraction/addition and multiplications in their linear counterparts by simple scaling operations in the logarithmic domain. Logarithmic pipeline A/D converters are more appropriate for high-frequency applications whereas logarithmic algorithmic A/D converters are particularly suitable for compact, low-cost designs. Examples are given to illustrate the proposed techniques.