Analytical Settling Noise Models of Single-Loop Sigma–Delta ADCs

Switched-capacitor integrators are the basic building components for sigma–delta $(\Sigma\Delta)$ modulators, and their incomplete charge transfer (settling problem) constitutes one of the dominant error sources in $\Sigma \Delta$ modulators. Due to the complexity of the settling problem, analytic models for related noises are nonexistent. In this brief, closed forms of settling error models are obtained and represented as functions of $\Sigma\Delta$ modulator system parameters. Both behavioral simulations and transistor-level circuit simulations are employed to verify these analytical models, and the results show that our analytical models are sufficiently accurate.