A High-Speed and EDP-Efficient Range-Matching Scheme for Packet Classification

A range-matching scheme for packet classification (PC) that greatly improves search speed is presented. It effectively reduces the energy delay product (EDP) and increases the storage efficiency by up to 2.5 times over conventional ternary content addressable memories (TCAMs) under typical PC rule sets. Simulation results show that the proposed 16-bit range-matching word (RMW) achieves a 1.53-ns search time, which is a 70.5% delay reduction over that by Kim The EDP index is also reduced to 45% that by Kim A 64 word $\times$ 144 bit prototype chip whose word circuit comprises two 16-bit RMWs, a 104-bit TCAM word, and an 8-bit filter implemented using a 3.3-V 0.35-$\mu\hbox{m}$ complementary metal–oxide–semiconductor (CMOS) process achieves a 2.5-ns range-matching delay time with an energy index of 28.7 fJ/bit/search for the total word circuit.