A noise-optimized LC-VCO and DTC

This paper presents a phase noise analysis for all-PMOS Voltage-Controlled Oscillators (VCOs) in 1/f
²
region. A closed-form equation for VCO phase noise is derived as an auxiliary optimization tool for designers. The maximum operating frequency of divide-by-two circuit (DTC) is predicted to help reduce the phase noise introduced by the DTC. Based on the derived formulas, size optimization for noise performance of VCO and DTC is possible. Also, the DTC can generate IQ signal. In order to reduce the noise arose from the upconversion of flicker noise and thermal noise in current tail, a parallel LC circuit resonating at twice the VCO frequency is inserted between the cross-coupled pair and PMOS tail. The simulation results show that the VCO has a phase noise of -131dBc@1MHz offset with 2-GHz center frequency when consuming 4mA from a 3.3-V voltage supply. The DTC output improves the phase noise by 6dB while taking 500uA. The simulations are done with 0.35um CMOS models.