A 2 × 22Gb/s SFI5.2 CDR/deserializer in 65nm CMOS technology

A CDR/deserializer IC is designed in 65nm triple-well CMOS, dissipates 1.3W, receives two 20.6–22.3Gb/s (DQPSK) data channels, and outputs 4⊲1 × 10.65−11.3Gb/s SFI5.2 data and deskew channel. The deserializer comprises two limiting amplifiers, a 2 × 20G to 16 × 2.5G CDR/DEMUX, a synchronizing FIFO, SFI5.2 deskew channel generator, and a 5×2.5 to 10G MUX. It also includes a 5GHz PLL, a a 2.5Gb/s PRBS and BERT, a temperature sensor, and an I2C bus.