FPGA based asynchronous pipelined OFDM for MB-OFDM UWB application

Asynchronous pipelined circuits have many potential advantages over their synchronous equivalents including lower latency, lower power consumption, avoiding clock skew problem, etc., In this paper, asynchronous pipelined OFDM - a 128-point FFT/IFFT processor for FPGA-based MB-OFDM UWB system is considered for implementation. The advantage with this scheme is that instead of using Asynchronous FPGAs for implementing asynchronous circuits, Synchronous FPGAs which are available with low cost are used for implementing asynchronous circuits. The reason for choosing synchronous FPGAs is that these FPGAs are rich in registers and these registers are needed for the implementation of asynchronous pipelined circuits. Generally in asynchronous system, the global clock is replaced by a handshaking circuit. In the proposed technique, the FPGA based Muller C-elements are designed to generate various control signals in the handshaking circuit like REQuest and ACKnowledge, used to transfer the data from one block to the next block. To verify the efficacy of this approach, asynchronous pipelined OFDM is implemented on Stratix II ALTERA FPGA. The results are 100 % matched with the MATLAB results.