Gate-Recess Technology for InAs/AlSb HEMTs

The gate-recess technology for Si delta-doped InAs/AlSb high-electron-mobility transistors (HEMTs) has been investigated by combining atomic force microscopy (AFM) inspection of the gate-recess versus time with electrical device characterization. Deposition of the gate metal on the In
_0.5
Al
_0.5
As protection layer or on the underlying AlSb Schottky layer resulted in devices suffering from high gate-leakage current. Superior dc and high frequency device performance were obtained for HEMTs with an insulating layer between the gate and the Schottky layer resulting in a reduction of the gate leakage current I
_G
by more than two orders of magnitude at a drain-to-source voltage VDS of 0.1 V. The existence of this intermediate insulating layer was evident from the electrical measurements. AFM measurements suggested that the insulating layer was due to a native oxidation of the AlSb Schottky layer. The insulated-gate HEMT with a gate length of 225 nm exhibited a maximum drain current I
_D
higher than 500 mA/mm with good pinchoff characteristics, a dc transconductance g
_m
of 1300 mS/mm, and extrinsic values for cutoff frequency f
_T
and maximum frequency of oscillation f
_max
of 160 and 120 GHz, respectively.