Design of a 3 Bit 20 GS/s ADC in 65 nm CMOS

A 20 GS/s 3 bit flash ADC with an analog input bandwidth of 10 GHz is realized in a 65 nm LP CMOS technology. By employing a fourfold parallelization a high sample rate is achieved, while a large input bandwidth is maintained. Simulations at 20 GS/s exhibit an effective resolution of 2.5 Bits at the Nyquist frequency. The chip area is 5.2 mm
²
while the ADC core area is 0.16 mm
²
.