VHDL design of an ATM switch

An ATM switch must be capable of not only routing a user data cell from an input to an output port, it must also be capable of interpreting and processing ATM signalling and management cells. The VHDL design of an ATM layer switch meeting these requirements is discussed. The switching requirements of the different layers of the protocol model is presented based on standards documents. In addition, ways of dividing the functionality of the management and signalling planes are described with the goal of optimizing the performance of the ATM switching system.